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? liquid crystal displays group LQ035Q7DB03 tft lcd module (model no.: LQ035Q7DB03) spec. issue date: september 18, 2002 p roduc t s pecific a tions
records of revision 99?9e9?9? 9:9?9?9y99?99y9?9e9?9 3 9?99?9? 9: 9?9?9?9999t99y9? no. page summary note 2002.09 .18 9?9?9999t99y9? - - 1 st issue sharp ? ? ? ? notice this publication is the proprietary of sharp and is copyrighted, with all rights reserved. under the copyrig ht l aws, no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical for any purpose, in whole or in part, without the express written permission of sharp. expre ss written permission is also required before any use of this publication may be made by a third party. the application circuit examples in this publication are provided to explain the representative applications of s harp's devices and are not intended to guarantee any circuit design or permit any industrial property right or other rights to be executed. sharp takes no responsibility for any problems related to any industrial proper ty r ight or a third party resulting from the use of sharp's devices, except for those resulting directly from dev ice manufacturing processes. in the absence of confirmation by device specification sheets, sharp takes no responsibility for any defects th at o ccur in equipment using any of sharp's devices, shown in catalogs, data books, etc. contact sharp in order to obtain the latest device specification sheets before using any sharp's device. sharp reserves the right to make changes in the specifications, characteristics, data, materials, structures a nd o ther contents described herein at any time without notice in order to improve design or reliability. contact shar p in order to obtain the latest specification sheets before using any sharp's device. manufacturing locations are a lso subject to change without notice. observe the following points when using any device in this publication. sharp takes no responsibility for damage caused by improper use of the devices. the devices in this publication are designed for use in general electronic equipment designs, such as: ~ personal computers ~ office automation ~ telecommunication equipment ~ test and measurement equipment ~ industrial control ~ audio visual and multimedia equipment ~ consumer electronics the appropriate design measures should be taken to ensure reliability and safety when sharp's devices are used for equipment such as: ~ transportation control and safety equipment(i.e., aircraft, trains, automobiles, etc.) ~ traffic signals ~ gas leakage sensor breakers ~ alarm equipment ~ various safety devices etc. sharp's devices shall not be used for equipment that requires extremely high level of reliability, such as: ~ military and space applications ~ nuclear power control equipment ~ medical equipment for life support contact a sharp representative, in advance, when intending to use sharp's devices for any "specif ic" applications other than those recommended by sharp. contact and consult with a sharp representative if there are any questions about the contents of th is publication. sharp ? ? ? (1) application this literature applies to LQ035Q7DB03. (2) overview this module is a color reflective and active matrix lcd module incorporating amorphous silicon tft (thin film transistor), named ad-tft(advanced tft). it is composed of a color tft-lcd panel, driver ics, an fpc, a back light and a back sealed casing. it isn?t composed control circuit. graphics and texts can be displayed on a 240 3 320 dots panel with 262,144 colors by supplying. optimum view angle is 6 o?clock. an inverted display mode is selective in the vertical or the horizontal direction. 3 mechanical specifications table 1 parameter specifications units remarks screen size (diagonal) 8.9 [3.52 ? ] diagonal cm display active area 53.64 h 71.52 v mm pixel format 240(h) 320(v) (1 pixel = r+g+b dots) pixels pixel pitch 0.2235 h 0.2235 v mm pixel configuration r,g,b vertical stripe unit outline dimension 65.0(w) 85.0(h) 3.4 (d) mm 2 note3-1 3 mass 40 6 typ. surface hardness 3h 2 note 3-1 3 excluding protrusion. for detailed measurements and tolerances, please refer to fig. 1. (4)pixel configuration r g b display area fpc (240,1) (1,1) (240,320) (1,320) sharp ? ? ? (5)input/output terminal 5-1)tft-lcd panel driving section table2 pin no. symbol i/o description remarks 1 vdd power supply of gate driver(high level) 2 agnd 3 mod i control signal of gate driver 2 note5-1 3 4 mod i control signal of gate driver 2 note5-1 3 5 u/l i selection for vertical scanning direction 2 note5-2 3 6 sps i start signal of gate driver 7 cls i clock signal of gate driver 8agnd 9 vee power supply of gate driver(low level) 10 vee - power supply of gate driver(low level) 11 vcom i common electrode driving signal 12 vcom i common electrode driving signal 13 spl i/o sampling start signal 14 r0 i red data signal(lsb) 15 r1 i red data signal 16 r2 i red data signal 17 r3 i red data signal 18 r4 i red data signal 19 r5 i red data signal(msb) 20 g0 i green data signal(lsb) 21 g1 i green data signal 22 g2 i green data signal 23 g3 i green data signal 24 g4 i green data signal 25 g5 i green data signal(msb) 26 b0 i blue data signal(lsb) 27 b1 i blue data signal 28 b2 i blue data signal 29 b3 i blue data signal 30 b4 i blue data signal 31 b5 i blue data signal(msb) 32 vshd power supply of digital 33 dgnd ground(digital) 34 ps i power save signal (please don?t carry out use by ?low? fixation) 35 lp i data latch signal of source driver 36 dclk i data sampling clock signal 37 lbr i selection for horizontal scanning direction 2 note5-3 3 38 spr i/o sampling start signal 39 vsha power supply(analog) sharp ? ? ? ? pin no. symbol i/o description remarks 40 agnd ? 41 agnd ? 42 rev i reverse control signal 43 com o produce rev signal with the amplitude of agnd vsha 44 agnd ? 45 agnd ? 46 agnd ? 47 agnd ? 48 agnd ? 49 agnd ? 50 agnd ground(analog) 2 note5-1 3 see section(7-1)-(a) ? t cautions when you turn on or off the power supply?. 2 note5-2 3 selection for vertical scanning direction u/l scanning direction (pixel configuration) low normal scanning ( x , 1 ) ? ? ? ? ? ? ? ? ? ? ( x , 320 ) high inverted scanning ( x , 1) a ? ? ? ? ? ? ? ? ( x , 320) ? 2 note5-3 3 selection for horizontal scanning direction lbr spl spr scanning direction (pixel configuration) high input output normal scanning (1,y) (240,y) low output input inverted scanning (1,y) (240,y) 5-2)back light driving section table3 pin no. symbol i/o description remark 1 vl1 i power supply for led (high voltage) n.c 3 n.c 4 vl2 i power supply for led (low voltage) 5 n.c sharp ? ? ? (6)absolute maximum ratings table 4 parameter symbol condition ratings unit remark power supply(source/analog) vsha ta=25 ? -0.3 ? +7.0 v power supply(source/digital) vshd ta=25 ? -0.3 ? +7.0 v power supply (gate) vdd ta=25 ? -0.3 ? +35.0 v power supply (gate) vdd-vee ta=25 ? -0.3 ? +35.0 v input voltage (digital) vid ta=25 ? -0.3 ? vshd+0.3 v [terminal ? ] operating temperature (panel surface ) opp -10 ? 60 ?2 note6 3 storage temperature ) stg -25 ? 70 ?2 note6-2 3 [terminal ? ] mod,u/l,sps,cls,spl,r0 ? r5,g0 ? g5,b0 ? b5,lp,dclk,lbr,spr,ps,rev 2 note6-2 3 humidity: 95%rh max.(at ta ? 40 ? ). maximum wet-bulb temperature is less than 39 ? (at ta > 40 ? ). condensation of dew must be avoided. sharp ? ? y ? (7)electrical characteristics 7-1)recommended operating conditions a) tft-lcd panel driving section ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? table 5 ? ? ? ? ? ? ? ? ? ? gnd=0v parameter symbol min. typ. max. unit remarks supply voltage for source driver (analog) vsha +4.5 +5.0 +5.5 v supply voltage for source driver (digital) vshd +3.0 +3.3 +3.6 v supply voltage for gate driver high voltage vdd +14.5 +15.0 +15.5 v low voltage vee -10.5 -10.0 -9.5 v input voltage for source driver (low) vils gnd - 0.2vshd v 2 note 7-1 3 input voltage for source driver (high) vihs 0.8vshd - vshd v 2 note 7-1 3 input current for source driver (low) i ils --30 a 2 note 7-1 3 i ihs1 --30 a 2 note 7-2 3 input current for source driver (high) i ihs2 - - 1200 a 2 note 7-3 3 input voltage for gate driver (low) vilg gnd - 0.2vshd v 2 note 7-4 3 input voltage for gate driver (high) vihg 0.8vshd - vshd v 2 note 7-4 3 input current for gate driver (low) i ilg --4 a 2 note 7-4 3 input current for gate driver (high) i ihg --4 a 2 note 7-4 3 common electrode ac component vcomac - ? 2.5 ? 2.6 vp-p 2 note 7-5 3 driving signal dc component vcomdc -0.4 +0.6 +1.6 v 2 note 7-5 3 t ? cautions when you turn on or off the power supply ? ? turn on or off the power supply with simultaneously or the following sequence. turn on ? vshd vsha vee vdd turn off ? vdd vee vsha vshd ? ? the input signal of ?mod? terminals(pin no.3 and no.4) must be low voltage when turning on the power supply, and it is held until more than double vertical periods after vcc is turned on completely. after then, it must be held high voltage until turning off the power supply.(connect pin no.3 and no.4 terminals to the same signal.) 2 note 7-1 3 dclk,spl,spr,lbr,lp,ps,rev,r0 ? r5,g0 ? g5 and b0 ? b5 terminals are applied. 2 note 7-2 3 dclk,spl,spr,lbr,lp,rev,r0 ? r5,g0 ? g5 and b0 ? b5 terminals are applied. 2 note 7-3 3 ps terminal is applied. 2 note 7-4 3 mod,cls,sps and u/l terminals are applied. 2 note 7-5 3 vcomac should be alternated on vcomdc every 1 horizontal period and 1 vertical period. vcomdc bias is adjusted so as to minimize flicker or maximum contrast every each module . b) back light driving section table 6 ta=25 ? parameter symbol min typ max units remarks terminal led voltage v l 21.6 24 v led current i l 15 20 < a power consumption w l 0.324 w 2 note 7-6 3 2 note 7-6 3 calculated reference value(i l v l ) ? ? ? ? ? ? ? sharp ? ? t ? 7-2) timing characteristics of input signals table 7 ac characteristics (1) ? ? ? ? ? ? ? ? ? (vsha=+5v, vshd=+3.3v, ta=25 ? ) parameter symbol min. typ. max. unit remark clock frequency of source driver fck 4.5 6.8 mhz rising time of clock tcr 20 ns falling time of clock tcf 20 ns pulse width (high level) tcwh 40 ns pulse width (low level) tcwl 40 ns dclk frequency of start pulse fsp 16.5 28 khz setup time of start pulse tsusp 15 ns hold time of start pulse thsp 10 ns pulse width of start pulse twsp 1.5/f ck ns spl,spr 2 note 7-7 3 setup time of latch pulse tsulp 20 ns hold time of latch pulse thlp 20 ns lp pulse width of latch pulse twlp 60 ns setup time of ps tsups 0 59 s source driver hold time of ps thps 0 1 s ps set up time of data tsud 15 ns hold time of data thd 10 ns r0 ? r5,g0 ? g5 ,b0 ? b5 clock frequency fcls 16.5 28 khz pulse width of clock(low) twlcls 5 (1/fclk)-30 s pulse width of clock(high) twhcls 30 s rising time of clock trcls 100 ns falling time of clock tfcls 100 ns setup time of clock tsucls 3 s hold time of clock thcls 0 s cls frequency of start pulse fsps 50 86 hz setup time of start pulse tsu 100 ns hold time of start pulse th 300 ns rising time of start pulse trsp 100 ns gate driver falling time of start pulse tfsp 100 ns sps vcom setup time of vcom tsuvcom 3 s vcom hold time of vcom thvcom 1 s 2 note 7-7 3 there must be only one up-edge of dclk (includes tsusp and thsp time) in the period of spl=?hi?. sharp ? ? ? ? fig.(a) horizontal timing chart >37 ? :<:7 ? /:7 ? ? ? 5 e ? ? 5 e ? ? ? 5 e ? ? ? 5 ? >37 ? /37 ? :<37 ? :<+ ? /+ ? *>3 ? *>/ ? */ ? *9 ? >:7 ? >/ ? >3 ? /*3: ? :<*3: ? :<7: ? /7: ? :<=*64 ? /=*64 ? sharp ? ? ? fig.(b) vertical timing chart :<:7: ? >37 ? /37*2 ? /:7: ? 9*3: ? -*3: ? 9:7: ? -:7: ? |